package CPU.rv64_1stage

import CPU.common.SodorConfiguration
import chisel3._
import chisel3.util.experimental.BoringUtils

class DiffTestIO extends Bundle {
  val r = Output(Vec(32, UInt(32.W)))
//  val commit = Output(Bool())
//  val isMultiCommit = Output(Bool())
  val thisPC    = Output(UInt(32.W))
  val thisINST  = Output(UInt(32.W))
//  val isMMIO = Output(Bool())
//  val isRVC = Output(Bool())
//  val isRVC2 = Output(Bool())
//  val intrNO = Output(UInt(64.W))
//
//  val priviledgeMode = Output(UInt(2.W))
//  val mstatus = Output(UInt(64.W))
//  val sstatus = Output(UInt(64.W))
//  val mepc = Output(UInt(64.W))
//  val sepc = Output(UInt(64.W))
//  val mcause = Output(UInt(64.W))
//  val scause = Output(UInt(64.W))
}




class SodorTile(implicit val conf: SodorConfiguration) extends Module
{
  val io = IO(new Bundle {
    // val difftest = new DiffTestIO
  })
  val core   = Module(new Core())
  core.io := DontCare
  val memory = Module(new AsyncScratchPadMemory(num_core_ports = 2))
  core.io.dmem <> memory.io.core_ports(0)
  core.io.imem <> memory.io.core_ports(1)
  core.reset := reset.toBool
}

object u_sodortile {
  implicit val sodor_conf = SodorConfiguration()
  def main(args: Array[String]): Unit = {
    chisel3.Driver.execute(args, () => new SodorTile())
  }
}
